1. Field of the Invention
The present invention relates to a method for fabricating a capacitor for a semiconductor device, and in particular to an improved method for fabricating a capacitor for a semiconductor device which is capable of increasing an effective area of a capacitor by forming a dimple on a lower electrode of the capacitor.
2. Description of the Background Art
A DRAM cell is formed of one transistor and one capacitor. Therefore, in order to increase the integration density of a semiconductor memory device, a study has been intensively conducted for decreasing the area of a capacitor which is a unit device. At an initial stage of the development, the capacitor which was actually utilized for a commercial DRAM was a planer type, in which a dopant layer formed on a semiconductor substrate was used as a lower electrode, including a dielectric film and a conductive film formed on the semiconductor substrate. Recently, a 3-dimensional capacitor formed in a stackable type or trench type is disclosed, which is capable of decreasing the area of a capacitor mounted on a semiconductor device and increasing the capacitance of the capacitor. The above-described 3-dimensional capacitor is widely used.
However, there is a limit for increasing the capacitance using a 3-dimensional capacitor. Namely, in order to decrease the area on the capacitor occupied by the capacitor and increase the capacitance of the capacitor, the height of the capacitor should be increased or a deep trench should be formed on the semiconductor substrate. Therefore, the process may be damaged due to the wiring error during a wiring process, in which the unit devices of the semiconductor device are connected, and the coating problems. In order to overcome the above-described problems, a semicircular silicon film is formed on the surface of the node electrode of the capacitor for thereby forming an embossed portion thereon, so that the effective area of the lower electrode of the capacitor is increased for thereby increasing the capacitance of the capacitor.
The fabrication method of a capacitor using a known HSG film will be explained with reference to FIGS. 1A through 1C. Namely, as shown in FIG. 1A, a plurality of capacitor lower electrodes 3 are formed on the semiconductor substrate 1. The method for forming the lower electrodes 3 of the capacitor will be explained. An insulation film 2 is formed on the semiconductor substrate 1, and the insulation film 2 is selectively etched for thereby exposing the surfaces of the semiconductor substrate 1. Next, a conductive film made of a polysilicon material is formed on the exposed surfaces of the semiconductor substrate 1 and the entire surfaces of the insulation film 2, and the resultant structure is patterned for thereby forming a conductive film pattern 3. The conductive film pattern 3 is a lower electrode 3 of the capacitor.
Next, as shown in FIG. 1B, a hemispherical grain (HSG) film 4a is formed on the upper surface of the lower electrode 3. A dielectric film 5 is formed on the upper surface of the HSG film 4a. An upper electrode 6 of the capacitor is formed on the upper surfaces of the dielectric film 5 and the insulation film 2 for thereby completing a fabrication process of the capacitor.
As shown in FIG. 1B, it is difficult to selectively form the HSG film 4a on the upper surface of the lower electrode 3. Therefore, in order to overcome the above-described problems, a HSG (Hemispherical grain) film is accumulatively formed on the front surface of the resultant structure as shown in FIG. 1A in a known manner. At this time, the insulation film 2 is formed of a material so that the HSG film is well accumulatively formed on the upper surface of the same. In this case, the HSG film is formed on the lower electrode 3 as well as the upper surface of the insulation film 2. However, since the HSG film is not well accumulatively formed on the insulation film 2, the HSG film formed on the upper surface is thinner than the HSG film 4a formed on the upper surface of the lower electrode 3. In addition to that, an electric short may occur between the neighboring lower electrodes 3 due to the HSG film. In order to prevent the above-described electric short, an anisotropical etching operation is performed with respect to the HSG film. At this time, the anisotropical etching operation is performed until the HSG film formed on the insulation film 2 is eliminated for thereby selectively eliminating the HSG film formed on the upper surface of the insulation film 2. However, in this manner, the HSG film formed on the upper surface of the insulation film 2, the HSG film 4a formed on the upper surface of the lower electrode 3 and the lower electrode may be damaged, so that it is difficult to obtain a desired capacitance of the capacitor, and a reproducibility of the product is decreased.
When forming the conductive film as shown in FIG. 1A, since the conductive film is formed even on the upper surface of the insulation film for filling the contact hole and forming the lower electrode of the capacitor, in the case that an aspect ratio of the contact hole is large, the process for filling the contact hole is not easily implemented.
In addition, in the process for forming and patterning the conductive film as shown in FIG. 1A and forming a lower electrode of the capacitor, if the step degree of the contact hole is large, the surface of the conductive film is not uniformly formed. Therefore, when forming a photoresist film on the ununiform conductive film and photo-etching the same, the pattern of the photoresist film is formed uniformly on the portions away from the focusing portions of the light exposing apparatus, so that a reliability of the semiconductor device is decreased because it is difficult to obtain a capacitor lower electrode of a fine pattern.